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Ordering number : EN*5120
CMOS LSI
LC89610
Mini-Disk Decoder LSI
Preliminary Overview
The LC89610 is a playback signal processing CMOS LSI that supports the mini-disk data format. Data that has been decoded by a CD decoder, an ACIRC decoder, or a CDROM decoder circuit is passed to a DRAM controller circuit and the LC89610 uses external DRAM to process shock proof. The shock proof processed data is passed to an audio data decoding LSI, the LC89602.
Package Dimensions
unit: mm 3181A-SQFP100
[LC89610]
Features
* EFM decoder and PLL clock generator * Detection, protection, and interpolation of the EFM frame synchronization signal * Servo command control * On-chip ACIRC decoder and ACIRC RAM * 8 frame jitter margin * Powerful error detection and correction (C1: dual errors, C2: quadruple errors) * CLV control using EFM and ADIP signals * Subcode Q decoding and CRC error checking * Shock proof memory using 1, 4, 16, or 64 Mbits of external DRAM * Buffering control and management for TOC and UTOC data * Buffering control and management for subdata * ADIP decoding and CRC error checking * Low-power design using a 0.8 m rule CMOS process * Support for low-voltage operation (VDD = 3.0 to 5.5 V) * CCB based CPU interface
SANYO: SQFP100
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
81095HA (OT) No. 5120-1/7
LC89610
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter Maximum supply voltage Input and output voltages Operating temperature Storage temperature Soldering conditions Symbol VDD max VI VO Topr Tstg 10 seconds (pins only) Ta = 25C Ta = 25C Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -30 to +70 -55 to +125 260 Unit V V C C C
Allowable Operating Ranges at Ta = -30 to +70C, VSS = 0 V
Parameter Supply voltage Input voltage Symbol VDD VIN Conditions min 3.0 0 typ max 5.5 VDD Unit V V
DC Characteristics at Ta = -30 to +70C, VSS = 0 V, VDD = 4.5 to 5.5 V
Parameter Input high level voltage Input low level voltage Input high level voltage Input low level voltage Input high level voltage Input low level voltage Output high level voltage Output low level voltage Output high level voltage Output low level voltage Output high level voltage Output low level voltage Input leakage current Output leakage current Pull-up resistance Quiescent current Quiescent current Symbol VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL VOH VOL IL IOZ RUP IDD IDD *1 *1 *2 *2 *3 *3 IOH = -1 mA, *4 IOL = 1 mA, *4 IOH = -1 mA, *5 IOL = 1 mA, *5 IOH = -3 mA, *6 IOL = 3 mA, *7 VI = VSS, VDD For high-impedance state outputs *8 *9 *10 -10 -10 10 20 0.1 250 VDD - 2.1 0.4 +10 +10 40 200 475 VDD - 1.0 1.0 VDD - 0.1 0.1 0.6 VDD 0.4 VDD 0.7 VDD 0.3 VDD Conditions min 0.8 VDD 0.2 VDD typ max Unit V V V V V V V V V V V V A A k A A
Note: 1. HFL, TES, CE, CL, SUBREQ, SREQ, RESET, ADIPCRI, BIDATAI, BICLKI 2. Inputs other than *1, 2, and 4 XIN. 3. EFMIN 4. PDO 5. EFMO 6. Outputs other than *5 and *6 XOUT, AO, and DO (open-drain output). 7. Outputs other than *5 and *6 XOUT, and AO. 8. For MD0 to MD3, TEST1 to TEST5. However, note that the pull-up resistors are not connected when the PULLSW pin is low. 9. When the PULLSW pin is low, outputs are open, and VI = VSS or VDD. 10.When the PULLSW pin is high, outputs are open, and VI = VSS or VDD.
No. 5120-2/7
LC89610 Block Diagram
No. 5120-3/7
LC89610 Pin Assignment
No. 5120-4/7
LC89610 Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Symbol MDP MDS FSW V/P TES TOFF TGL JP + JP - MAD3 MAD2 MAD1 MAD0 MAD9 MAD10 MAD11 VSS MRAS MWE MD1 MD0 MD3 MD2 MCAS MOE MAD8 MAD7 MAD6 MAD5 MAD4 SUBDO0 SUBDO1 SUBDO2 SUBDO3 SUBDO4 SUBDO5 SUBDO6 SUBDO7 16M VSS VDD XIN XOUT SUBREQ SUBWR SUBDTC SUBDEN TEST5 TEST4 TEST3 TESTO SD0 SD1 SD2 SD3 I/O O O O O I O O O O O O O O O O O -- O O I/O I/O I/O I/O O O O O O O O O O O O O O O O O -- -- I O I O O O I I I I O O O O CLV servo signal output CLV servo signal output CLV servo signal output CLV servo signal output Track jump signal input Track jump signal output Track jump signal output Track jump signal output Track jump signal output DRAM address output DRAM address output DRAM address output DRAM address output DRAM address output DRAM address output DRAM address output Ground DRAM RAS signal output DRAM WE signal output DRAM data I/O DRAM data I/O DRAM data I/O DRAM data I/O DRAM CAS signal output DRAM OE signal output DRAM address output DRAM address output DRAM address output DRAM address output DRAM address output Subdata and internal status output Subdata and internal status output Subdata and internal status output Subdata and internal status output Subdata and internal status output Subdata and internal status output Subdata and internal status output Subdata and internal status output 16.9344 MHz clock output VSS ground Power supply 16.9344 oscillator input 16.9344 oscillator output Subdata request signal input Subdata transfer clock output Subdata transfer complete signal output Subdata enable output Test input (normally tied to VDD) Test input (normally tied to VDD) Test input (normally tied to VDD) Test output Sound block data output Sound block data output Sound block data output Sound block data output Function
Continued on next page. No. 5120-5/7
LC89610
Continued from preceding page.
Pin No. 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol SD4 SD5 SD6 SD7 SWR SACK SEPF SREQ CL CE DI DO WRQ INT RESET CCB SYNCOK EMONT EMON0 EMON1 PCK FSEQ VSS ADIPSYN ADIPCRC PULLSW SBSW VDD 4.2M TEST2 PREPIT EFMI EFMO VDD VSS ADIPCRI BICLKI BIDATAI HFL TEST1 AO AI VSS PDO MON I/O O O O O O O O I I I I O O O I I O O O O O O -- O O I I -- I I I I O -- -- I I I I O O I O -- O Sound block data output Sound block data output Sound block data output Sound block data output Sound block data transfer clock output Sound block data acknowledge signal output Sound block data empty signal output Sound block data request signal input CPU interface data transfer clock input CPU interface chip enable signal input CPU interface data input CPU interface data output CPU interface interrupt signal output CPU interface interrupt signal output System reset CPU interface type switching input Sector synchronization detection signal output Error detection monitor signal output Error detection monitor signal output Error detection monitor signal output 4.3218 MHz monitor signal output Frame synchronization detection signal output Ground (for the on-chip DRAM only) ADIP synchronization timing signal output ADIP data CRC flag output Internal pull-up resistor switching signal input Subdata/internal status switching signal input Power supply (for the on-chip DRAM only) Test input (normally tied to VDD) Test input (normally tied to VDD) CLV servo output signal switching input HF signal input EFM signal output Power supply Ground ADIP carrier signal input Bi-phase data transfer clock input Bi-phase data input Track detection signal input 4.2336 MHz output VCO control signal output VCO control signal input VCO control signal output Ground CLV servo signal output Function
No. 5120-6/7
LC89610
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1995. Specifications and information herein are subject to change without notice. PS No. 5120-7/7

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